1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same and, more particularly, to a MOS transistor with a recessed gate and a method of fabricating the same.
2. Description of the Related Art
In general when the length of a transistor gate is reduced to a level approaching 0.1 μm or thereabout, several problems can occur. The problems that occur include rolling off of the threshold voltage, decrease of the punch-through voltage due to a short channel effect (SCE) and so on. In order to suppress the short channel effect, one can (a) reduce the junction depth of a source and a drain, or (b) increase the effective channel length. The structure of a metal oxide semiconductor (MOS) transistor with a recessed gate is such that it allows one to implement both of the above listed methods at the same time.
FIG. 1 is a plan view of a typical MOS transistor with a recessed gate. Referring to FIG. 1, an active region 11 is defined by a trench isolation layer 11a formed in a semiconductor substrate. A recessed gate 30 is formed to intersect the active region 11. One portion of the active region 11 adjacent to the gate 30 is a source region 13, and another portion of the active region 11 at the other side of gate 30 is a drain region 15. One portion of the active region 11 which is overlapped by the gate 30 is a channel region 17.
FIGS. 2 and 3 are sectional views which illustrate the structure of the MOS transistor taken along the lines of I–I′ and II–II′ of FIG. 1 respectively. Referring to FIG. 2, the recessed gate 30 is located in a shallow trench formed in a semiconductor substrate 10. The active regions adjacent to the recessed gate 30 are the source region 13 and the drain region 15, and the active region under the recessed gate 30 is the channel region 17. A gate insulating layer 20 is interposed between the recessed gate 30 and the channel region 17. The depth of the recessed gate 30 is deeper than the depth of the source/drain region 13, 15, therefore the effective channel length L can be lengthened.
Referring to FIG. 3, the channel region 17 is located between the trench isolation layers 11a. The source region 13 (FIG. 1) and the drain region 15 (FIG. 1) are located at the front and the back of the channel region 17 respectively, and the recessed gate 30 is located on the channel region 17. As shown in the drawing, the recessed gate 30 has a positive slopped sidewall and the trench isolation layers 11a also have a positive slopped sidewall. As a result, as shown in FIG. 3, the above structure creates a sharp tip 17a in the channel region 17 at which the recessed gate 30 and the trench isolation layer 11a adjoin each other. Referring to FIG. 1, the sharp tip 17a is formed along the boundary between the channel region 17 and the trench isolation layer 11a. As a result, when such a MOS transistor works, a channel is formed not only under the recessed gate 30, and but also in the sharp tip 17a. The channel formed in the sharp tip 17a can reduce the effective channel length of the MOS transistor with the recessed gate 30. Therefore, the MOS transistor with the recessed gate may result in a failure to suppress the short channel effect.